Intelligent reconfigurable universal fuzzy flip-flop

نویسندگان
چکیده

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Parameter optimisation in fuzzy flip-flop-based neural networks

This paper presents a method for optimizing the parameters of Multilayer Perceptron Neural Networks (MLP NN) consisting of fuzzy flip-flops (F3) based on various operations using Bacterial Memetic Algorithm with the Modified Operator Execution Order (BMAM). In early work, the authors proposed the gradient based Levenberg-Marquardt (LM) algorithm for variable optimization. The BMAM local and glo...

متن کامل

An Analysis of D-Fuzzy Flip-Flop Design

The paper presents the concept of existing D fuzzy flip-flop design and analyses the working of the design. The existing design has been studied for its delay parameters and variability. Comparisons with the previous designs has been done to lay down the superiority of the fuzzy design over existing binary flip-flop designs. Keywords— Binary flip-flop, Fuzzy flip-flop, D fuzzy flip-flop, delay,...

متن کامل

Flip-Flop Nets

The so-called synthesis problem for nets which consists in deciding whether a given automaton is isomorphic to the case graph of a net and then constructing the net has been solved for various type of nets ranging from elementary nets to Petri nets. Though P/T nets admits polynomial time synthesis algorithms, the synthesis problem for elementary nets is known to be NP-complete. Applying the pri...

متن کامل

Flip Flop Circuit Using Cmos

flip-flop circuit technique has been designed. CMOS new flip-flop circuit with CMOS domino logic which, All the flip-flops were designed using UMC 180. Recognize standard circuit symbols for D Type flip-flops. though can be largely prevented by using the Edge Triggered D Type flipflop illustrated in Fig 5.3.3. locked loop, using 32 nm CMOS technology. Here we design D flipflop for Phase locked ...

متن کامل

Load-Sensitive Flip-Flop Characterization

Different flip-flop designs vary in the number and complexity of logic stages they contain, and hence have different inherent parasitic delays and output drive strengths. We examine the effect of electrical load on flip-flop delay and energy consumption and show that the relative ranking of optimized flip-flop structures varies widely with both electrical effort and absolute load. We also show ...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

ژورنال

عنوان ژورنال: IEICE Electronics Express

سال: 2010

ISSN: 1349-2543

DOI: 10.1587/elex.7.1119